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1CYW2331
PRELIMINARY
CYW2331
Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers
Features
* Operating voltage: 2.7V to 5.5V * PLL1 operating frequency: -- 2.0 GHz with prescaler ratios of 64/65 and 128/129 * PLL2 operating frequency: -- 600 MHz with prescaler ratios of 8/9 and 16/17 * Lock detect feature * Available in a 20-pin TSSOP (Thin Shrink Small Outline Package) * Available in a 24-pin CSP (Chip Scale Package) * Available in a 20-pin MLF (Mirco Lead Frame Package)
Applications
The Cypress CYW2331 is a dual serial input PLL frequency synthesizer which includes a 2.0-GHz RF and a 600-MHz IF dual modulus prescaler to combine the RF and IF mixer frequency sections of wireless communication systems. The synthesizer is designed for cordless/cellular telephone systems, cable TV tuners, WLANs and other wireless communication systems. The device operates from 2.7V and dissipates only 24 mW.
CYW2331 Dual Hi-Lo PLL Block Diagram
GND (4) GND (7) VCC1 (1) VCC2 (20) VP1 (2)
FIN1 (5) FIN1# (6)
Prescaler 64/65 or 128/129
Binary 7-Bit Swallow Counter
Binary 11-Bit Programmable Counter
fp1 Phase Detector Charge Pump
DOPLL1 (3)
19-Bit Latch OSC_IN (8)
Pwr-dwn PLL1 fr1 fr fp Monitor Output Selector
15-Bit Reference Counter Latch Selector LE (13) DATA (12) CLOCK (11) 20-Bit Latch 20-Bit Latch 15-Bit Reference Counter 19-Bit Latch Pwr-dwn PLL2
FO/LD (10)
fr2
Cntrl 22-Bit Shift Reg.
Power Control
FIN2 (16) FIN2# (15)
Prescaler 8/9 or 16/17
Binary 4-Bit Swallow Counter
Binary 11-Bit Programmable Counter
Phase Detector fp2
Charge Pump
DOPLL2 (18)
GND (14)
GND (9)
GND (17)
VP2 (19)
Pin Configuration
Vcc1 Vcc2
Vp1
24
23
18
17
DOPLL1 GND FIN1 FIN1# GND OSC_IN GND FO/LD
3 4 5 6 7 8 9 10
18 17 16 15 14 13 12 11
DOPLL2 GND FIN2 FIN2# GND LE DATA CLOCK
DoPLL1 GND Fin1 Fin1# GND OSC_IN NC
3 4 5 6 7 8 10 11 12 9
19 18
GND Fin2 Fin2# GND LE DATA NC
DoPLL1 GND Fin1 Fin1# GND
16
Vp1
2
19
DoPLL2
1 2 3 4 5
20
VP1
2
19
VP2
22
NC
1
21 20
NC
Vp2
VCC1
1
20
VCC2
DoPLL2
Vp2
Vcc1
Vcc2
15 14
GND Fin2 Fin2# GND LE
(Top View)
17 16 15 14 13
(Top View)
13 12 11
Fo/LD
CLOCK
OSC_IN
TSSOP
CSP
MLF
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 February 12, 2001. Rev. **
CLOCK
Fo/LD
DATA
GND
GND
10
6
7
8
9
PRELIMINARY
Pin Definitions
Pin Name VCC1 Pin No. (TSSOP) 1 Pin No. (CSP) 24 Pin No. (MLF) 19 Pin Type P Pin Description
CYW2331
Power Supply Connection for PLL1 and PLL2: When power is removed from both the VCC1 and VCC2 pins, all latched data is lost. PLL1 Charge Pump Rail Voltage: This voltage accommodates VCO circuits with tuning voltages higher than the VCC of PLL1. PLL1 Charge Pump Output: The phase detector gain is IP/2. Sense polarity can be reversed by setting the FC bit in software (via the Shift Register). Input to PLL1 Prescaler: Maximum frequency 2.0 GHz. Complementary Input to PLL1 Prescaler: A bypass capacitor should be placed as close as possible to this pin and must be connected directly to the ground plane. Oscillator Input: This input has a VCC/2 threshold and CMOS logic level sensitivity. Lock Detect Pin of PLL1 Section: This output is HIGH when the loop is locked. It is multiplexed to the output of the programmable counters or reference dividers in the test program mode. (Refer to Table 3 for configuration.) Data Clock Input: One bit of data is loaded into the Shift Register on the rising edge of this signal. Serial Data Input Load Enable: On the rising edge of this signal, the data stored in the Shift Register is latched into the reference counter and configuration controls, PLL1 or PLL2 depending on the state of the control bits. Complementary Input to PLL2 Prescaler: A bypass capacitor should be placed as close as possible to this pin and must be connected directly to the ground plane. Input to PLL2 Prescaler: Maximum frequency 600 MHz. PLL2 Charge Pump Output: The phase detector gain is IP/2. Sense polarity can be reversed by setting the FC bit in software (via the Shift Register). PLL2 Charge Pump Rail Voltage: This voltage accommodates VCO circuits with tuning voltages higher than the VCC of PLL2. Power Supply Connections for PLL1 and PLL2: When power is removed from both the VCC1 and VCC2 pins, all latched data is lost. Analog and Digital Ground Connections: This pin must be grounded. No Connect
VP1 DOPLL1
2 3
2 3
20 1
P O
FIN1 FIN1#
5 6
5 6
3 4
I I
OSC_IN FO/LD
8 10
8 11
6 8
I O
CLOCK DATA LE
11 12 13
12 14 15
9 10 11
I I I
FIN2#
15
17
13
I
FIN2 DOPLL2
16 18
18 20
14 16
I O
VP2 VCC2
19 20
22 23
17 18
P P
GND
4, 7, 9, 14, 17 N/A
4, 7, 10, 16, 19 1, 9, 13, 21
2, 5, 7, 12, 15 N/A
G
N/C
N/C
2
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating Parameter VCC or VP VOUT IOUT TL TSTG Output Voltage Output Current Lead Temperature Storage Temperature Description Power Supply Voltage
CYW2331
only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +6.5 -0.5 to VCC+0.5 15 +260 -55 to +150 Unit V V mA C C
Handling Precautions
Devices should be transported and stored in antistatic containers. These devices are static sensitive. Ensure that equipment and personnel contacting the devices are properly grounded. Cover workbenches with grounded conductive mats.
Always turn off power before adding or removing devices from system. Protect leads with a conductive sheet when handling or transporting PC boards with devices. If devices are removed from the moisture protective bags for more than 36 hours, they should be baked at 85C in a moisture free environment for 24 hours prior to assembly in less than 24 hours.
Recommended Operating Conditions
Parameter VCC1, VCC2 VP TA Description Power Supply Voltage Charge Pump Voltage Operating Temperature Ambient air at 0 CFM flow Test Condition Rating 2.7 to 5.5 VCC to +5.5 -40 to +85 Unit V V C
3
PRELIMINARY
Electrical Characteristics: VCC = VP = 2.7V to 5.5V, TA = -40C to +85C, Unless otherwise specified
Parameter ICC IPD FIN1 FIN2 FOSC F PFIN1 PFIN2 VOSC IIH, IIL VIH VIL IIH IIL VOH VOL IDOH(SO) IDOL(SO) IDOH(SI) IDOL(SI) IDO High/Low Level Input Current High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High level Output Voltage Low Level Output Voltage IDO High, Source Current IDO Low, Source Current IDO High, Sink Current IDO Low, Sink Current IDO Charge Pump Sink and Source Mismatch Charge Pump Current Variation vs. Temperature VCC = VP = 3.0V, [IIDO(SI)I - IIDO(SO)I]/ [1/2*{IIDO(SI)]I+IIDO(SO)I}]*100% -40CCYW2331
Max.
Unit mA
25 2000 600 45 10 4 4 4 100
A MHz MHz MHz MHz dBm dBm dBm VP-P A V
VCC * 0.2 -10 -10 VCC * 0.8 VCC * 0.2 -3.8 -1 3.8 1 3 15 0.5 0.5 10 10
V A A V V mA mA mA mA %
IDO vs T IOFF
5 2.5
% nA
Charge Pump High-ImVCC = VP = 3.0V pedance Leakage Current
Note: 1. IDOvs T; Charge pump current variation vs. temperature. [IIDO(SI)@TI - IIDO(SI)@25 CI]/IIDO(SI)@25CI * 100% and [IIDO(SO)@TI - IIDO(SO)@25CI]/IIDO(SO)@25CI *100%.
4
PRELIMINARY
Timing Waveforms
Key:
CYW2331
FC Bit HIGH FC Bit LOW (Refer to Table 2 for meaning of FC bit.) Increasing Frequency VCO Characteristics Phase Comparator Sense
Increasing Voltage
Phase Detector Output Waveform
FR
FP tw tw
LD
DO Charge Pump Output Current Waveform
FR
FP tw tw
Do
IDO
High-Impedance State
5
PRELIMINARY
Timing Waveforms (continued)
Serial Data Input Timing Waveform[2, 3, 4, 5]
// DATA PD = MSB PRE // B1 A7 // // CNT2 CNT1 = LSB
CYW2331
CLOCK t1
// t2
//
t3
t4
t5
LE
//
// t6
//
//
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data as described in Table 1. Table 1. Control Configuration CNT1 0 0 1 1 CNT2 0 1 0 1 Function Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector polarity, set current in PLL2, set PLL2 to Hi-Impedance state, set monitor selector to PLL2. Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector polarity, set current in PLL1, set PLL1 to Hi-Impedance state, set monitor selector to PLL1 Program Counter for PLL2: A = 0 to 15, B = 3 to 2047, set PLL2 prescaler ratio, set PLL2 to power-down. Program Counter for PLL1: A = 0 to 127, B = 3 to 2047, set PLL1 prescaler ratio, set PLL1 to power-down.
Notes: 2. t1-t5 = t > 0.5 s. 3. CLOCK may remain HIGH after latching in data. 4. DATA is shifted in with the MSB first. 5. For DATA definitions, refer to Table 2.
6
PRELIMINARY
Table 2. Shift Register Configuration[6] 1 2 3 4 R2 5 R3 6 R4 7 R5 8 R6 9 R7 10 R8 11 12 13 14 15 16 17 18 19
CYW2331
20 TS
21 LD
22 FO
Reference Counter and Configuration Bits
CNT1 CNT2 R1
R9 R10 R11 R12 R13 R14 R15 FC IDO
Programmable Counter Bits
CNT1 CNT2 A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 PRE PD
Bit(s) Name CNT1, CNT2 R1-R15 FC IDO TS LD FO PRE PD
Function Control Bits: Directs programming data to PLL1 (high frequency) or PLL2 (low frequency). Reference Counter Setting Bits: 15 bits, R = 3 to 32767.[7] Phase Sense of the Phase Detector: Set to match the VCO polarity, H = + (Positive VCO transfer function). Charge Pump Setting Bit: IDO HIGH = 3.8 mA, IDO LOW = 1 mA at VP = 3V. Hi-Impedance State Bit: Makes DO High-Impedance for PLL1 and PLL2 when HIGH. Lock Detect: Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when locked. When not locked, this pin is LOW. Frequency Out: This bit can be set to read out reference or programmable divider at the LD pin for test purposes. Prescaler Divide Bit: For PLL1: LOW = 64/65 and HIGH = 128/129. For PLL2: LOW = 8/9 and HIGH = 16/17. Power-down: LOW = power-up and HIGH = power-down. FIN is at a high-impedance state, respective B counter is disabled, forces DO outputs to Hi-Impedance and phase comparators are disabled. The reference counter is disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be input and latched in the power-down state. Swallow Counter Divide Ratio: A = 0 to 127 for PLL1 and 0 to 15 for PLL2. Programmable Counter Divide Ratio: B = 3 to 2047.[7]
A1-A7 B1-B11
Table 3. FO/LD Pin Truth Table FO (Bit 22) PLL1 0 0 0 0 0 1 0 1 1 1 1 PLL2 0 0 0 0 1 0 1 0 1 1 1 PLL1 0 0 1 1 X X X X 0 1 1 LD (Bit 21) PLL2 0 1 0 1 0 0 1 1 1 0 1 Disable PLL2 Lock Detect PLL1 Lock Detect PLL1/PLL2 Lock Detect PLL2 Reference Divider Output PLL1 Reference Divider Output PLL2 Programmable Divider Output PLL1 Programmable Divider Output PLL2 Counter Reset PLL1 Counter Reset PLL1/PLL2 Counter Reset FO/LD Pin Output State
Notes: 6. The MSB is loaded in first. 7. Low count ratios may violate frequency limits of the phase detector.
7
PRELIMINARY
Table 4. 7-Bit Swallow Counter (A) Truth Table[8] Divide Ratio A PLL1 (High Frequency) 0 1 ::: 126 127 PLL2 (Low Frequency) 0 1 ::: 14 15 X X ::: X X X X ::: X X X X ::: X X 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 0 0 ::: 1 1 A7 A6 A5 A4 A3 A2
CYW2331
A1 0 1 ::: 0 1 0 1 ::: 0 1
Table 5. 11-Bit Programmable Counter (B) Truth Table[9] Divide Ratio B 3 4 ::: 2046 2047 B11 0 0 ::: 1 1 B10 0 0 ::: 1 1 B9 0 0 ::: 1 1 B8 0 0 ::: 1 1 B7 0 0 ::: 1 1 B6 0 0 ::: 1 1 B5 0 0 ::: 1 1 B4 0 0 ::: 1 1 B3 0 1 ::: 1 1 B2 1 0 ::: 1 1 B1 1 0 ::: 0 1
Table 6. 15-Bit Programmable Reference Counter (for PLL1 and PLL2) Truth Table[9] Divide Ratio R 3 4 ::: 32766 32767 R15 0 0 ::: 1 1 R14 0 0 ::: 1 1 R13 0 0 ::: 1 1 R12 0 0 ::: 1 1 R11 0 0 ::: 1 1 R10 0 0 ::: 1 1 R9 0 0 ::: 1 1 R8 0 0 ::: 1 1 R7 0 0 ::: 1 1 R6 0 0 ::: 1 1 R5 0 0 ::: 1 1 R4 0 0 ::: 1 1 R3 0 1 ::: 1 1 R2 1 0 ::: 1 1 R1 1 0 ::: 0 1
Ordering Information[10]
Ordering Code CYW2331 Package Name ZI BCI LFI Package Type 20-pin Thin Shrink Small Outline Package (0.173" wide) 24-pin Chip Scale Package (3.5 mm X 4.5 mm) 20-pin Micro Lead Frame (4 mm x 4 mm) Tape and Reel Option TR
Notes: 8. B is greater than or equal to A. 9. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation: fvco = {(P * B) + A} * fosc / R where (A < B) fvco: Output frequency of the external VCO. fosc: The crystal reference oscillator frequency. A: Preset divide ratio of the 7-bit swallow counter (0 to 127) and the 4-bit swallow counter (0 to 15). B: Preset ratio of the 11-bit programmable counter (3 to 2047). P: Preset divide ratio of the dual modulus prescaler. R: Preset ratio of the 15-bit programmable reference counter (3 to 32767). The divide ratio N = (P * B) + A. 10. Operating temperature range: -40C to +85C.
Document #: 38-00967-**
8
PRELIMINARY
Typical Performance Characteristics
Charge P um p Current vs D o Voltage Icp=High
6
CYW2331
Charge P um p Current vs D o Voltage Icp=Low
1 .5
V p=5V
4
Vp=3V
1
Vp=5V
V p=3V
2
Do Current (mA)
0 .5
Do Current (mA)
0
Vp=3V Vp = 5V
0
-2
-0 .5
V p=3V V p = 5V
-4
-1
-6 0
1
2
D o Voltage (V)
3
4
5
-1 .5
0
1
2
D o Voltage (V)
3
4
5
Figure 1. Do Output Current High Mode
Figure 3. Do Output Current Low Mode
ATTEN 10dB RL -2.5dBm
VAVG 10dB/
100
MKR 100.0kHz
-85.50dB
8 5 dB c
1
2
START RBW 835.8505MHz 3.0kHz STOP VBW 3.0kHz 836.1505MHz SWP 84.0ms
4 3
Figure 3. PLL Reference Spurs Figure 2. PLL Reference Spurious Level is -85.5 dBc
Marker Reference Real Number Marker 1 Marker 2 Marker 3 Marker 4 623 21 14 13
Imaginar y Input Frequency 100 MHz -823 -120 -55 -39 1 GHz 1.8 GHz 2.2 GHz
Figure 4. Input Impedance FIN1, FIN2
9
PRELIMINARY
Package Diagram
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173" wide)
CYW2331
10
PRELIMINARY
Package Diagram
CYW2331
24-Pin Chip Scale Package (CSP 3.5 mm X 4.5 mm)
f d 0.20 4X
0.10
Z
Z 3.50 PIN 1 PAD CORNER X d 0.10 Z
4.50
Y
1.040.10 0.700.05
TOP VIEW
SIDE VIEW
PIN 1 PAD CORNER
22
24
21
1
0.45 X 0.25 TYP j 0.15 m ZXY
0.50
ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M-1994. UNLESS OTHERWISE SPECIFIED
4X 0.25 13 9
12
10
0.50 4X 1.25
BOTTOM VIEW
11
PRELIMINARY
Package Diagram
CYW2331
20-Pin Micro Lead Frame Package (MLF 4 mm X 4 mm)
2X 0.25 A D D/2 D1 D1/2 2X N 5 6 0.25 C B 4X P 0.50 DIA. 1 2 3 E1 E 4X Q E1/2 E/2 1 2 3 E2 (Ne-1)Xe REF. 10 0.05 A A1 A2 A3 N C 4X P b R D2 D2/2 8. 4 0.10
M
C
A
CA B
L 0.20 2X 0.20 2X CA CB B 0 C SEATING PLANE e (Nd-1)Xe REF.
E2/2
TOP VIEW
CC C L C L 4 b A1 11
BOTTOM VIEW
SECTION "C-C"
e e SCALE: NONE
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
PACKAGE OUTLINE, MLF2, 4X4mm BODY
S Y M B O L
COMMON DIMENSIONS MIN. NOM. MAX.
0.00 0.85 0.01 0.65 0.20 REF. 4.00 BSC 3.75 BSC 4.00 BSC 3.75 BSC 0.42 0.17 0.50 BSC 20 5 5 0.60 0.23 0.40 1.70 1.70 1.00 0.05 0.80
NOTES:
N O T E
1. DIE THICKNESS ALLOWABLE IS 0.305mm MAXIMUM(.012 INCHES MAXIMUM) 2. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. - 1994. 3. N IS THE NUMBER OF TERMINALS. Nd IS THE NUMBER OF TERMINALS IN X-DIRECTION & Ne IS THE NUMBER OF TERMINALS IN Y-DIRECTION. 4. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20 AND 0.25mm FROM TERMINAL TIP. 5. THE PIN #1 IDENTIFIER MUST BE EXISTED ON THE TOP SURFACE OF THE PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF PACKAGE BODY. 6. 7. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL. ALL DIMENSIONS ARE IN MILLIMETERS. THE SHAPE SHOWN ON FOUR CORNERS ARE NOT ACTUAL I/O. PACKAGE WARPAGE MAX 0.05mm.
A A1 A2 A3 D D1 E E1 0 P R e N Nd Ne L b Q D2 E2
11
0.24 0.13
12 0.60 0.23 3 3 3 0.75 0.30 0.65 1.85 1.85 4
8. 9.
0.50 0.18 0.30 1.55 1.55
10. APPLIED FOR EXPOSED PAD AND TERMINALS. EXCLUDE EMBEDDING PART OF EXPOSED PAD FROM MEASURING. 11. APPLIED ONLY FOR TERMINALS.
(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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